/***************************************************************************
 *                                - io80C51RC.h -
 *
 * Special header for the Intel 80C51RC Microcontroller.
 *
 ***************************************************************************/

#ifndef IO80C51RC_H
#define IO80C51RC_H
#define __80C51RC__
#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#pragma language=extended

/* After is STC additional SFR or change */

__sfr __no_init volatile unsigned char AUXR @ 0x8e;
/* __sfr __no_init volatile unsigned char  IPH   @ 0xb7; */

/* Watchdog Timer Register */
__sfr __no_init volatile unsigned char WDT_CONTR @ 0xe1;

/* ISP_IAP_EEPROM Register */
__sfr __no_init volatile unsigned char ISP_DATA  @ 0xe2;
__sfr __no_init volatile unsigned char ISP_ADDRH @ 0xe3;
__sfr __no_init volatile unsigned char ISP_ADDRL @ 0xe4;
__sfr __no_init volatile unsigned char ISP_CMD   @ 0xe5;
__sfr __no_init volatile unsigned char ISP_TRIG  @ 0xe6;
__sfr __no_init volatile unsigned char ISP_CONTR @ 0xe7;

/* System Clock Divider */
__sfr __no_init volatile unsigned char CLK_DIV  @ 0xc7;

/* I_O Port Mode Set Register */
__sfr __no_init volatile unsigned char P0M0  @ 0x93;
__sfr __no_init volatile unsigned char P0M1  @ 0x94;
__sfr __no_init volatile unsigned char P1M0  @ 0x91;
__sfr __no_init volatile unsigned char P1M1  @ 0x92;
__sfr __no_init volatile unsigned char P2M0  @ 0x95;
__sfr __no_init volatile unsigned char P2M1  @ 0x96;
__sfr __no_init volatile unsigned char P3M0  @ 0xb1;
__sfr __no_init volatile unsigned char P3M1  @ 0xb2;

/* SPI Register */
__sfr __no_init volatile unsigned char SPSTAT  @ 0x84;
__sfr __no_init volatile unsigned char SPCTL   @ 0x85;
__sfr __no_init volatile unsigned char SPDAT   @ 0x86;

/* ADC Register */
__sfr __no_init volatile unsigned char ADC_CONTR  @ 0xc5;
__sfr __no_init volatile unsigned char ADC_DATA   @ 0xc6;
__sfr __no_init volatile unsigned char ADC_LOW2   @ 0xbe;

/* PCA SFR */
//__sfr __no_init volatile unsigned char CCON   @ 0xD8;
__sfr __no_init volatile unsigned char CMOD   @ 0xD9;
__sfr __no_init volatile unsigned char CCAPM0 @ 0xDA;
__sfr __no_init volatile unsigned char CCAPM1 @ 0xDB;
__sfr __no_init volatile unsigned char CCAPM2 @ 0xDC;
__sfr __no_init volatile unsigned char CCAPM3 @ 0xDD;
__sfr __no_init volatile unsigned char CCAPM4 @ 0xDE;
__sfr __no_init volatile unsigned char CCAPM5 @ 0xDF;

__sfr __no_init volatile unsigned char CL     @ 0xE9;
__sfr __no_init volatile unsigned char CCAP0L @ 0xEA;
__sfr __no_init volatile unsigned char CCAP1L @ 0xEB;
__sfr __no_init volatile unsigned char CCAP2L @ 0xEC;
__sfr __no_init volatile unsigned char CCAP3L @ 0xED;
__sfr __no_init volatile unsigned char CCAP4L @ 0xEE;
__sfr __no_init volatile unsigned char CCAP5L @ 0xEF;

__sfr __no_init volatile unsigned char CH     @ 0xF9;
__sfr __no_init volatile unsigned char CCAP0H @ 0xFA;
__sfr __no_init volatile unsigned char CCAP1H @ 0xFB;
__sfr __no_init volatile unsigned char CCAP2H @ 0xFC;
__sfr __no_init volatile unsigned char CCAP3H @ 0xFD;
__sfr __no_init volatile unsigned char CCAP4H @ 0xFE;
__sfr __no_init volatile unsigned char CCAP5H @ 0xFF;

__sfr __no_init volatile unsigned char PCA_PWM0 @ 0xF2;
__sfr __no_init volatile unsigned char PCA_PWM1 @ 0xF3;
__sfr __no_init volatile unsigned char PCA_PWM2 @ 0xF4;
__sfr __no_init volatile unsigned char PCA_PWM3 @ 0xF5;
__sfr __no_init volatile unsigned char PCA_PWM4 @ 0xF6;
__sfr __no_init volatile unsigned char PCA_PWM5 @ 0xF7;

__sfr __no_init volatile union
{
    unsigned char CCON; /* B Register */
    struct /* B Register */
    {
        unsigned char CCF0 : 1;
        unsigned char CCF1 : 1;
        unsigned char CCF2 : 1;
        unsigned char CCF3 : 1;
        unsigned char CCF4 : 1;
        unsigned char CCF5 : 1;
        unsigned char CR : 1;
        unsigned char CF : 1;
    } CCON_bit;
} @ 0xD8;


/*-------------------------------------------------------------------------
 *   8051 Core
 *-------------------------------------------------------------------------*/

__sfr __no_init volatile union
{
    unsigned char ACC; /* Accumulator */
    struct /* Accumulator */
    {
        unsigned char ACC0 : 1;
        unsigned char ACC1 : 1;
        unsigned char ACC2 : 1;
        unsigned char ACC3 : 1;
        unsigned char ACC4 : 1;
        unsigned char ACC5 : 1;
        unsigned char ACC6 : 1;
        unsigned char ACC7 : 1;
    } ACC_bit;
} @ 0xE0;
__sfr __no_init volatile union
{
    unsigned char PSW; /* Program Status Word */
    struct /* Program Status Word */
    {
        unsigned char P : 1;
        unsigned char F1 : 1;
        unsigned char OV : 1;
        unsigned char RS0 : 1;
        unsigned char RS1 : 1;
        unsigned char F0 : 1;
        unsigned char AC : 1;
        unsigned char CY : 1;
    } PSW_bit;
} @ 0xD0;

__sfr __no_init volatile unsigned char SP @ 0x81; /* Stack Pointer */
__sfr __no_init volatile unsigned char DPL @ 0x82; /* Data Pointer Low byte, LSB of DPTR */
__sfr __no_init volatile unsigned char DPH @ 0x83; /* Data Pointer High byte, MSB of DPTR */
__sfr __no_init volatile union
{
    unsigned char B; /* B Register */
    struct /* B Register */
    {
        unsigned char B0 : 1;
        unsigned char B1 : 1;
        unsigned char B2 : 1;
        unsigned char B3 : 1;
        unsigned char B4 : 1;
        unsigned char B5 : 1;
        unsigned char B6 : 1;
        unsigned char B7 : 1;
    } B_bit;
} @ 0xF0;
__sfr __no_init volatile unsigned char WDTRST @ 0xA6; /* WatchDog Timer Reset */

/*-------------------------------------------------------------------------
 *   Timers
 *-------------------------------------------------------------------------*/

__sfr __no_init volatile unsigned char TL2 @ 0xCC; /* Timer2 Low */
__sfr __no_init volatile union
{
    unsigned char T2MOD; /* Timer 2 Mode Control */
    struct /* Timer 2 Mode Control */
    {
        unsigned char DCEN : 1;
        unsigned char T2OE : 1;
        unsigned char  : 1;
        unsigned char  : 1;
        unsigned char  : 1;
        unsigned char  : 1;
        unsigned char  : 1;
        unsigned char  : 1;
    } T2MOD_bit;
} @ 0xC9;
__sfr __no_init volatile unsigned char TH0 @ 0x8C; /* Timer0 High */
__sfr __no_init volatile union
{
    unsigned char TCON; /* Timer Control */
    struct /* Timer Control */
    {
        unsigned char IT0 : 1;
        unsigned char IE0 : 1;
        unsigned char IT1 : 1;
        unsigned char IE1 : 1;
        unsigned char TR0 : 1;
        unsigned char TF0 : 1;
        unsigned char TR1 : 1;
        unsigned char TF1 : 1;
    } TCON_bit;
} @ 0x88;
__sfr __no_init volatile unsigned char TH2 @ 0xCD; /* Timer2 High */
__sfr __no_init volatile unsigned char TH1 @ 0x8D; /* Timer1 High */
__sfr __no_init volatile union
{
    unsigned char TMOD; /* Timer Mode */
    struct /* Timer Mode */
    {
        unsigned char M00 : 1;
        unsigned char M10 : 1;
        unsigned char C_T0 : 1;
        unsigned char GATE0 : 1;
        unsigned char M01 : 1;
        unsigned char M11 : 1;
        unsigned char C_T1 : 1;
        unsigned char GATE1 : 1;
    } TMOD_bit;
} @ 0x89;
__sfr __no_init volatile unsigned char RCAP2L @ 0xCA; /* Timer2 Capture low */
__sfr __no_init volatile unsigned char RCAP2H @ 0xCB; /* Timer2 Capture high */
__sfr __no_init volatile unsigned char TL0 @ 0x8A; /* Timer0 Low */
__sfr __no_init volatile unsigned char T2CON @ 0xC8; /* Timer2 Control */
__sfr __no_init volatile unsigned char TL1 @ 0x8B; /* Timer1 Low */

/*-------------------------------------------------------------------------
 *   Interrupt
 *-------------------------------------------------------------------------*/

__sfr __no_init volatile union
{
    unsigned char IP; /* Interrupt Priority */
    struct /* Interrupt Priority */
    {
        unsigned char PX0 : 1;
        unsigned char PT0 : 1;
        unsigned char PX1 : 1;
        unsigned char PT1 : 1;
        unsigned char PS : 1;
        unsigned char PT2 : 1;
        unsigned char  : 1;
        unsigned char  : 1;
    } IP_bit;
} @ 0xB8;
__sfr __no_init volatile union
{
    unsigned char IE; /* Interrupt Enable */
    struct /* Interrupt Enable */
    {
        unsigned char EX0 : 1;
        unsigned char ET0 : 1;
        unsigned char EX1 : 1;
        unsigned char ET1 : 1;
        unsigned char ES : 1;
        unsigned char EADC_SPI : 1;
        unsigned char EPCA_LVD : 1;
        unsigned char EA : 1;
    } IE_bit;
} @ 0xA8;
__sfr __no_init volatile union
{
    unsigned char IPH; /* Interrupt Priority High */
    struct /* Interrupt Priority High */
    {
        unsigned char PX0H : 1;
        unsigned char PT0H : 1;
        unsigned char PX1H : 1;
        unsigned char PT1H : 1;
        unsigned char PSH : 1;
        unsigned char PT2H : 1;
        unsigned char  : 1;
        unsigned char  : 1;
    } IPH_bit;
} @ 0xB7;

/*-------------------------------------------------------------------------
 *   I/O Port
 *-------------------------------------------------------------------------*/

__sfr __no_init volatile union
{
    unsigned char P1; /* Port 1 */
    struct /* Port 1 */
    {
        unsigned char P10 : 1;
        unsigned char P11 : 1;
        unsigned char P12 : 1;
        unsigned char P13 : 1;
        unsigned char P14 : 1;
        unsigned char P15 : 1;
        unsigned char P16 : 1;
        unsigned char P17 : 1;
    } P1_bit;
} @ 0x90;
__sfr __no_init volatile union
{
    unsigned char P0; /* Port 0 */
    struct /* Port 0 */
    {
        unsigned char P00 : 1;
        unsigned char P01 : 1;
        unsigned char P02 : 1;
        unsigned char P03 : 1;
        unsigned char P04 : 1;
        unsigned char P05 : 1;
        unsigned char P06 : 1;
        unsigned char P07 : 1;
    } P0_bit;
} @ 0x80;
__sfr __no_init volatile union
{
    unsigned char P3; /* Port 3 */
    struct /* Port 3 */
    {
        unsigned char RxD : 1;
        unsigned char TxD : 1;
        unsigned char P32 : 1;
        unsigned char P33 : 1;
        unsigned char P34 : 1;
        unsigned char P35 : 1;
        unsigned char P36 : 1;
        unsigned char P37 : 1;
    } P3_bit;
} @ 0xB0;
__sfr __no_init volatile union
{
    unsigned char P2; /* Port 2 */
    struct /* Port 2 */
    {
        unsigned char P20 : 1;
        unsigned char P21 : 1;
        unsigned char P22 : 1;
        unsigned char P23 : 1;
        unsigned char P24 : 1;
        unsigned char P25 : 1;
        unsigned char P26 : 1;
        unsigned char P27 : 1;
    } P2_bit;
} @ 0xA0;

/*-------------------------------------------------------------------------
 *   Serial I/O Port
 *-------------------------------------------------------------------------*/

__sfr __no_init volatile unsigned char SBUF @ 0x99; /* Serial Data Buffer */
__sfr __no_init volatile unsigned char SADEN @ 0xB9; /* Slave address mask */
__sfr __no_init volatile unsigned char SADDR @ 0xA9; /* Slave address */
__sfr __no_init volatile union
{
    unsigned char SCON; /* Serial Control */
    struct /* Serial Control */
    {
        unsigned char RI : 1;
        unsigned char TI : 1;
        unsigned char RB8 : 1;
        unsigned char TB8 : 1;
        unsigned char REN : 1;
        unsigned char SM2 : 1;
        unsigned char SM1 : 1;
        unsigned char SM0 : 1;
    } SCON_bit;
} @ 0x98;

/*-------------------------------------------------------------------------
 *   System Management
 *-------------------------------------------------------------------------*/

__sfr __no_init volatile union
{
    unsigned char PCON; /* Power Control */
    struct /* Power Control */
    {
        unsigned char IDL : 1;
        unsigned char PD : 1;
        unsigned char GF0 : 1;
        unsigned char GF1 : 1;
        unsigned char POF : 1;
        unsigned char  : 1;
        unsigned char SMOD0 : 1;
        unsigned char SMOD1 : 1;
    } PCON_bit;
} @ 0x87;
/*
 * Interrupt Vectors
 */
#define extern0 0x03 /* External interrupt 0 */
#define IE0_int 0x03 /* External interrupt 0 */
#define TF0_int 0x0B /* Timer 0 Interrupt */
#define timer0 0x0B /* Timer 0 Interrupt */
#define IE1_int 0x13 /* External interrupt 1 */
#define extern1 0x13 /* External interrupt 1 */
#define TF1_int 0x1B /* Timer 1 Interrupt */
#define timer1 0x1B /* Timer 1 Interrupt */
#define TI_int 0x23 /* Serial Port Interrupt */
#define SerialTI 0x23 /* Serial Port Interrupt */
#define RI_int 0x23 /* Serial Port Interrupt */
#define SerialRE 0x23 /* Serial Port Interrupt */
#define SerialInt 0x23 /* Serial Port Interrupt */

#pragma language=default
#endif  /* __IAR_SYSTEMS_ICC__  */

/***************************************************************************
 *   Assembler definitions
 *
 *   The following SFRs are built in in the a8051.exe and can not be
 *   defined explicitly in this file:
 *     ACC,B,PSW,SP,DPL,DPH
 *   The PSW-bits are built-in in the a8051.exe
 *     OV,AC,F0,RS0,RS1,P
 *
 ***************************************************************************/

#ifdef __IAR_SYSTEMS_ASM__


/*-------------------------------------------------------------------------
 *   8051 Core
 *-------------------------------------------------------------------------*/

AUXR DEFINE 0x8E /* Auxiliary Register */
WDTRST DEFINE 0xA6 /* WatchDog Timer Reset */

/*-------------------------------------------------------------------------
 *   Timers
 *-------------------------------------------------------------------------*/

TCON DEFINE 0x88 /* Timer Control */
TCON_IT0 DEFINE 0x88.0
TCON_IE0 DEFINE 0x88.1
TCON_IT1 DEFINE 0x88.2
TCON_IE1 DEFINE 0x88.3
TCON_TR0 DEFINE 0x88.4
TCON_TF0 DEFINE 0x88.5
TCON_TR1 DEFINE 0x88.6
TCON_TF1 DEFINE 0x88.7
TMOD DEFINE 0x89 /* Timer Mode */
TL0 DEFINE 0x8A /* Timer0 Low */
TL1 DEFINE 0x8B /* Timer1 Low */
TH0 DEFINE 0x8C /* Timer0 High */
TH1 DEFINE 0x8D /* Timer1 High */
T2CON DEFINE 0xC8 /* Timer2 Control */
T2MOD DEFINE 0xC9 /* Timer 2 Mode Control */
RCAP2L DEFINE 0xCA /* Timer2 Capture low */
RCAP2H DEFINE 0xCB /* Timer2 Capture high */
TL2 DEFINE 0xCC /* Timer2 Low */
TH2 DEFINE 0xCD /* Timer2 High */

/*-------------------------------------------------------------------------
 *   Interrupt
 *-------------------------------------------------------------------------*/

IE DEFINE 0xA8 /* Interrupt Enable */
IE_EX0 DEFINE 0xA8.0
IE_ET0 DEFINE 0xA8.1
IE_EX1 DEFINE 0xA8.2
IE_ET1 DEFINE 0xA8.3
IE_ES DEFINE 0xA8.4
IE_ET2 DEFINE 0xA8.5
IE_EA DEFINE 0xA8.7
IPH DEFINE 0xB7 /* Interrupt Priority High */
IP DEFINE 0xB8 /* Interrupt Priority */
IP_PX0 DEFINE 0xB8.0
IP_PT0 DEFINE 0xB8.1
IP_PX1 DEFINE 0xB8.2
IP_PT1 DEFINE 0xB8.3
IP_PS DEFINE 0xB8.4
IP_PT2 DEFINE 0xB8.5

/*-------------------------------------------------------------------------
 *   I/O Port
 *-------------------------------------------------------------------------*/

P0 DEFINE 0x80 /* Port 0 */
P0_P00 DEFINE 0x80.0
P0_P01 DEFINE 0x80.1
P0_P02 DEFINE 0x80.2
P0_P03 DEFINE 0x80.3
P0_P04 DEFINE 0x80.4
P0_P05 DEFINE 0x80.5
P0_P06 DEFINE 0x80.6
P0_P07 DEFINE 0x80.7
P1 DEFINE 0x90 /* Port 1 */
P1_T2 DEFINE 0x90.0
P1_T2EX DEFINE 0x90.1
P2 DEFINE 0xA0 /* Port 2 */
P2_AD8 DEFINE 0xA0.0
P2_AD9 DEFINE 0xA0.1
P2_AD10 DEFINE 0xA0.2
P2_AD11 DEFINE 0xA0.3
P2_AD12 DEFINE 0xA0.4
P2_AD13 DEFINE 0xA0.5
P2_AD14 DEFINE 0xA0.6
P2_AD15 DEFINE 0xA0.7
P3 DEFINE 0xB0 /* Port 3 */
P3_RxD DEFINE 0xB0.0
P3_TxD DEFINE 0xB0.1
P3_INT0 DEFINE 0xB0.2
P3_INT1 DEFINE 0xB0.3
P3_T0 DEFINE 0xB0.4
P3_T1 DEFINE 0xB0.5
P3_WR DEFINE 0xB0.6
P3_RD DEFINE 0xB0.7

/*-------------------------------------------------------------------------
 *   Serial I/O Port
 *-------------------------------------------------------------------------*/

SCON DEFINE 0x98 /* Serial Control */
SCON_RI DEFINE 0x98.0
SCON_TI DEFINE 0x98.1
SCON_RB8 DEFINE 0x98.2
SCON_TB8 DEFINE 0x98.3
SCON_REN DEFINE 0x98.4
SCON_SM2 DEFINE 0x98.5
SCON_SM1 DEFINE 0x98.6
SCON_SM0 DEFINE 0x98.7
SBUF DEFINE 0x99 /* Serial Data Buffer */
SADDR DEFINE 0xA9 /* Slave address */
SADEN DEFINE 0xB9 /* Slave address mask */

/*-------------------------------------------------------------------------
 *   System Management
 *-------------------------------------------------------------------------*/

PCON DEFINE 0x87 /* Power Control */

#endif /* __IAR_SYSTEMS_ASM__*/
#endif /* IO80C51RC_H */
